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This paper presents a novel approach for test generation and test schedulingfor multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposedfor testing cores. Furthermore, a heuristic for selecting cores to be testedconcurrently and order of applying test patterns is proposed. Experimentalresults show that the proposed heuristics give us an optimized method for multiclock domain SoC testing in comparison with the previous works.

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint