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In recent years, Convolutional Neural Networks (ConvNets) have become anenabling technology for a wide range of novel embedded Artificial Intelligencesystems. Across the range of applications, the performance needs varysignificantly, from high-throughput video surveillance to the very low-latencyrequirements of autonomous cars. In this context, FPGAs can provide a potentialplatform that can be optimally configured based on the different performanceneeds. However, the complexity of ConvNet models keeps increasing making theirmapping to an FPGA device a challenging task. This work presents fpgaConvNet,an end-to-end framework for mapping ConvNets on FPGAs. The proposed frameworkemploys an automated design methodology based on the Synchronous Dataflow (SDF)paradigm and defines a set of SDF transformations in order to efficientlyexplore the architectural design space. By selectively optimising forthroughput, latency or multiobjective criteria, the presented tool is able toefficiently explore the design space and generate hardware designs fromhigh-level ConvNet specifications, explicitly optimised for the performancemetric of interest. Overall, our framework yields designs that improve theperformance by up to 6.65x over highly optimised embedded GPU designs for thesame power constraints in embedded environments.

fpgaConvNet: A Toolflow for Mapping Diverse Convolutional Neural Networks on Embedded FPGAs