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By advances in technology, integrated circuits have come to include morefunctionality and more complexity in a single chip. Although methods of testinghave improved, but the increase in complexity of circuits, keeps testing achallenging problem. Two important challenges in testing of digital circuitsare test time and accessing the circuit under test (CUT) for testing. Thesechallenges become even more important in complex system on chip (SoC) zone.This paper presents a multistage test strategy to be implemented on a BISTarchitecture for reducing test time of a simple core as solution for moreglobal application of SoC testing strategy. This strategy implements its testpattern generation and output response analyzer in a BILBO architecture. Theproposed method benefits from an irregular polynomial BILBO (IP-BILBO)structure to improve its test results. Experimental results on ISCAS-89benchmark circuits show an average of 35% improvement in test time inproportion to pervious work.

BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding