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Advanced hydrogen lithography techniques and low-temperature epitaxialovergrowth enable patterning of highly phosphorus-doped silicon (Si:P)monolayers (ML) with atomic precision. This approach to device fabrication hasmade Si:P monolayer systems a testbed for multiqubit quantum computingarchitectures and atomically precise 2-D superlattice designs whose behaviorsare directly tied to the deterministic placement of single dopants. However,dopant segregation, diffusion, surface roughening, and defect formation duringthe encapsulation overgrowth introduce large uncertainties to the exact dopantplacement and activation ratio. In this study, we develop a unique method bycombining dopant segregation/diffusion models with sputter profiling simulationto monitor and control, at the atomic scale, dopant movement usingroom-temperature grown locking layers (LL). We explore the impact of LL growthrate, thickness, rapid thermal anneal, surface accumulation, and growth frontroughness on dopant confinement, local crystalline quality, and electricalactivation within Si:P 2-D systems. We demonstrate that dopant movement can bemore efficiently suppressed by increasing the LL growth rate than by increasingLL thickness. We find that the dopant segregation length can be suppressedbelow a single Si lattice constant by increasing LL growth rates at roomtemperature while maintaining epitaxy. Although dopant diffusivity within theLL is found to remain high even below the hydrogen desorption temperature, wedemonstrate that exceptionally sharp dopant confinement with high electricalquality within Si:P monolayers can be achieved by combining a high LL growthrate with a low-temperature LL rapid thermal anneal.

Quantifying Atom-scale Dopant Movement and Electrical Activation in Si:P Monolayers