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Many modern video processing pipelines rely on edge-aware (EA) filteringmethods. However, recent high-quality methods are challenging to run inreal-time on embedded hardware due to their computational load. To this end, wepropose an area-efficient and real-time capable hardware implementation of ahigh quality EA method. In particular, we focus on the recently proposedpermeability filter (PF) that delivers promising quality and performance in thedomains of HDR tone mapping, disparity and optical flow estimation. We presentan efficient hardware accelerator that implements a tiled variant of the PFwith low on-chip memory requirements and a significantly reduced externalmemory bandwidth (6.4x w.r.t. the non-tiled PF). The design has been taped outin 65 nm CMOS technology, is able to filter 720p grayscale video at 24.8 Hz andachieves a high compute density of 6.7 GFLOPS/mm2 (12x higher than embeddedGPUs when scaled to the same technology node). The low area and bandwidthrequirements make the accelerator highly suitable for integration into SoCswhere silicon area budget is constrained and external memory is typically aheavily contended resource.

Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS