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Dynamic partial reconfiguration (DPR) allows one region of anfield-programmable gate array (FPGA) fabric to be reconfigured withoutaffecting the operations on the rest of the fabric. To use an FPGA as adynamically shared compute resource, one could partition and manage an FPGAfabric as multiple DPR partitions that can be independently reconfigured atruntime with different application function units (AFUs). Unfortunately,dividing a fabric into DPR partitions with fixed boundaries causes theavailable fabric resources to become fragmented. An AFU of a given size cannotbe loaded unless a sufficiently large DPR partition was floorplanned at buildtime. To overcome this inefficiency, we devised an "amorphous" DPR techniquethat is compatible with current device and tool support but does not requirethe DPR partition boundaries to be a priori fixed. A collection of AFUbitstreams can be simultaneously loaded on the fabric if their footprints (theactual area used by an AFU) in the fabric do not overlap. We verified thefeasibility of amorphous DPR on Xilinx Zynq System-on-Chip (SoC) FPGAs usingVivado. We evaluated the benefits of amorphous DPR in the context of adynamically reconfigurable vision processing pipeline framework.

Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation