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Efficient and real time segmentation of color images has a variety ofimportance in many fields of computer vision such as image compression, medicalimaging, mapping and autonomous navigation. Being one of the mostcomputationally expensive operation, it is usually done through software imple-mentation using high-performance processors. In robotic systems, however, withthe constrained platform dimensions and the need for portability, low powerconsumption and simultaneously the need for real time image segmentation, weenvision hardware parallelism as the way forward to achieve higheracceleration. Field-programmable gate arrays (FPGAs) are among the best suitedfor this task as they provide high computing power in a small physical area.They exceed the computing speed of software based implementations by breakingthe paradigm of sequential execution and accomplishing more per clock cycleoperations by enabling hardware level parallelization at an architecturallevel. In this paper, we propose three novel architectures of a well knownEfficient Graph based Image Segmentation algorithm. These proposedimplementations optimizes time and power consumption when compared to softwareimplementations. The hybrid design proposed, has notable furtherance ofacceleration capabilities delivering atleast 2X speed gain over other implemen-tations, which henceforth allows real time image segmentation that can bedeployed on Mobile Robotic systems.

FPGA based Parallelized Architecture of Efficient Graph based Image Segmentation Algorithm