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Hierarchical Temporal Memory is a new machine learning algorithm intended tomimic the working principle of neocortex, part of the human brain, which isresponsible for learning, classification, and making predictions. Although manyworks illustrate its effectiveness as a software algorithm, hardware design forHTM remains an open research problem. Hence, this work proposes an architecturefor HTM Spatial Pooler and Temporal Memory with learning mechanism, whichcreates a single image for each class based on important and unimportantfeatures of all images in the training set. In turn, the reduction in thenumber of templates within database reduces the memory requirements andincreases the processing speed. Moreover, face recognition analysis indicatesthat for a large number of training images, the proposed design provides higheraccuracy results (83.5\%) compared to only Spatial Pooler design presented inthe previous works.

On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory