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Modern embedded technology is a driving factor in satellite miniaturization,contributing to a massive boom in satellite launches and a rapidly evolving newspace industry. Miniaturized satellites, however, suffer from low reliability,as traditional hardware-based fault-tolerance (FT) concepts are ineffective foron-board computers (OBCs) utilizing modern systems-on-a-chip (SoC). Therefore,larger satellites continue to rely on proven processors with large featuresizes. Software-based concepts have largely been ignored by the space industryas they were researched only in theory, and have not yet reached the level ofmaturity necessary for implementation. We present the first integral,real-world solution to enable fault-tolerant general-purpose computing withmodern multiprocessor-SoCs (MPSoCs) for spaceflight, thereby enabling their usein future high-priority space missions. The presented multi-stage approachconsists of three FT stages, combining coarse-grained thread-level distributedself-validation, FPGA reconfiguration, and mixed criticality to assurelong-term FT and excellent scalability for both resource constrained andcritical high-priority space missions. Early benchmark results indicate adrastic performance increase over state-of-the-art radiation-hard OBC designsand considerably lower software- and hardware development costs. This approachwas developed for a 4-year European Space Agency (ESA) project, and we areimplementing a tiled MPSoC prototype jointly with two industrial partners.

Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-Stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft