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Asynchronous circuits employing delay-insensitive codes for datarepresentation i.e. encoding and following a 4-phase return-to-zero protocolfor handshaking are generally robust. Depending upon whether a singledelay-insensitive code or multiple delay-insensitive code(s) are used for dataencoding, the encoding scheme is called homogeneous or heterogeneousdelay-insensitive data encoding. This article proposes a new latency optimizedearly output asynchronous ripple carry adder (RCA) that utilizes single-bitasynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs)which incorporate redundant logic and are based on the delay-insensitivedual-rail code i.e. homogeneous data encoding, and follow a 4-phasereturn-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA),and carry select adder (CSLA) designs, which are based on homogeneous orheterogeneous delay-insensitive data encodings which correspond to theweak-indication or the early output timing model, the proposed early outputasynchronous RCA that incorporates SAFAs and DAFAs with redundant logic isfound to result in reduced latency for a dual-operand addition operation. Inparticular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2stages of SAFAs leads to reduced latency. The theoretical worst-case latenciesof the different asynchronous adders were calculated by taking into account thetypical gate delays of a 32/28nm CMOS digital cell library, and a comparison ismade with their practical worst-case latencies estimated. The theoretical andpractical worst-case latencies show a close correlation....

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding