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Processing-in-memory (PIM) architectures have seen an increase in popularityrecently, as the high internal bandwidth available within 3D-stacked memoryprovides greater incentive to move some computation into the logic layer of thememory. To maintain program correctness, the portions of a program that areexecuted in memory must remain coherent with the portions of the program thatcontinue to execute within the processor. Unfortunately, PIM architecturescannot use traditional approaches to cache coherence due to the high off-chiptraffic consumed by coherence messages, which, as we illustrate in this work,can undo the benefits of PIM execution for many data-intensive applications. Wepropose LazyPIM, a new hardware cache coherence mechanism designed specificallyfor PIM. Prior approaches for coherence in PIM are ill-suited to applicationsthat share a large amount of data between the processor and the PIM logic.LazyPIM uses a combination of speculative cache coherence and compressedcoherence signatures to greatly reduce the overhead of keeping PIM coherentwith the processor, even when a large amount of sharing exists.We find thatLazyPIM improves average performance across a range of data-intensive PIMapplications by 19.6%, reduces off-chip traffic by 30.9%, and reduces energyconsumption by 18.0%, over the best prior approaches to PIM coherence.

LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures