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Even the quantum simulation of simple molecules such as Fe$_2$S$_2$ requiresmore than 10$^6$ qubits. In order to assess such a multimillion scale ofidentical qubits and control lines, the silicon platform seems to be one of themost indicated routes as it provides the capability of nanometric, serial andindustrial quality fabrication. The maximum amount of quantum information perunit surface and the consequent space constraints on qubit operations are keyparameters towards fault-tolerant quantum information processing (QIP) with Siqubits. Such maximum density of quantum information is expressed for thecompact exchange-only Si double quantum dot qubit architecture as a function ofthe CMOS technology node. The size scale optimizing both physical qubitoperation time and quantum error correction (QEC) requirements is assessed byreviewing the physical and technological constraints. We determine the workableoperation frequency range of a Si-CMOS quantum processor to be within 1 and 100GHz, which limits its feasibility only to the most advanced nodes. Thecompatibility with classical control circuitry is discussed, focusing on thecryogenic CMOS operation required to bring the classical controller as close aspossible to the quantum processor and to enable interfacing thousands of qubitson the same chip. The operation time range prospected for cryogenic controlelectronics is found to be compatible with the qubit operation time. Bycombining the forecast of technology development with operation time andclassical circuitry constraints, we derive a maximum quantum informationdensity for logical qubits of 2.8 and 4 Mqb/cm$^2$ for the 10-nm and 7-nmtechnology nodes respectively for the Steane code. The density is one and twoorders of magnitude less for surface and concatenated codes respectively. Suchvalues provide a benchmark for the development of Si-based fault tolerant QIP.

Quantum information density scaling and qubit operation time constraints of CMOS silicon based quantum computer architectures