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This paper investigates the problem of implementing proportionate-type LMSfamily of algorithms in hardware for sparse adaptive filtering applicationsespecially the network echo cancelation. We derive a re-formulatedproportionate type algorithm through algorithm-architecture co-designmethodology that can be pipelined and has an efficient architecture forhardware implementation. We study the convergence, steady-state and trackingperformances of these re-formulated algorithms for white, color and speechinputs before implementing them in hardware. To the best of our knowledge thisis the first attempt to implement proportionate-type algorithms in hardware. Weshow that Delayed $\mu$-law Proportionate LMS (DMPLMS) algorithm for whiteinput and Delayed Wavelet MPLMS (DWMPLMS) for colored input are the robust VLSIsolutions for network echo cancellation where the sparsity of the echo pathscan vary with time. We implemented all the designs considering $16$-bit fixedpoint representation in hardware, synthesized the designs and synthesis resultsshow that DMPLMS algorithm with $\approx25\%$ increase in hardware overconventional DLMS architecture, achieves $3X$ improvement in convergence ratefor white input and DWMPLMS algorithm with $\approx58\%$ increase in hardwareachieves $15X$ improvement in convergence rate for correlated input conditions.

Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification