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Chip designers outsource chip fabrication to external foundries, but at therisk of IP theft. Logic locking, a promising solution to mitigate this threat,adds extra logic gates (key gates) and inputs (key bits) to the chip so that itfunctions correctly only when the correct key, known only to the designer butnot the foundry, is applied. In this paper, we identify a new vulnerability inall existing logic locking schemes. Prior attacks on logic locking have assumedthat, in addition to the design of the locked chip, the attacker has access toa working copy of the chip. Our attack does not require a working copy and yetwe successfully recover a significant fraction of key bits from the design ofthe locked chip only. Empirically, we demonstrate the success of our attack oneight large benchmark circuits from a benchmark suite that has been tailoredspecifically for logic synthesis research, for two different logic lockingschemes. Then, to address this vulnerability, we initiate the study of provablysecure logic locking mechanisms. We formalize, for the first time to ourknowledge, a precise notion of security for logic locking. We establish thatany locking procedure that is secure under our definition is guaranteed tocounter our desynthesis attack, and all other such known attacks. We thendevise a new logic locking procedure, Meerkat, that guarantees that the lockedchip reveals no information about the key or the designer's intendedfunctionality. A main insight behind Meerkat is that canonical representationsof boolean functionality via Reduced Ordered Binary Decision Diagrams (ROBDDs)can be leveraged effectively to provide security. We analyze Meerkat withregards to its security properties and the overhead it incurs. As such, ourwork is a contribution to both the foundations and practice of securing digitalICs.

Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism