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In this paper, we offer and discuss three efficient structural solutions forthe hardware-oriented implementation of discrete quaternion Fourier transformbasic operations with reduced implementation complexities. The first solution:a scheme for calculating sq product, the second solution: a scheme forcalculating qt product, and the third solution: a scheme for calculating sqtproduct, where s is a so-called i-quaternion, t is an j-quaternion, and q is anusual quaternion. The direct multiplication of two usual quaternions requires16 real multiplications (or two-operand multipliers in the case of fullyparallel hardware implementation) and 12 real additions (or binary adders). Atthe same time, our solutions allow to design the computation units, whichconsume only 6 multipliers plus 6 two input adders for implementation of sq orqt basic operations and 9 binary multipliers plus 6 two-input adders and 4four-input adders for implementation of sqt basic operation.

Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors