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To avoid packet loss and deadlock scenarios that arise due to faults or powergating in multicore and many-core systems, the network-on-chip needs to possessresilient communication and load-balancing properties. In this work, weintroduce the Fashion router, a self-monitoring and self-reconfiguring designthat allows for the on-chip network to dynamically adapt to component failures.First, we introduce a distributed intelligence unit, called Self-AwarenessModule (SAM), which allows the router to detect permanent component failuresand build a network connectivity map. Using local information, SAM adapts tofaults, guarantees connectivity and deadlock-free routing inside the maximalconnected subgraph and keeps routing tables up-to-date. Next, to reconfigurenetwork links or virtual channels around faulty/power-gated components, we addbidirectional link and unified virtual channel structure features to theFashion router. This version of the router, named Ex-Fashion, further mitigatesthe negative system performance impacts, leads to larger maximal connectedsubgraph and sustains a relatively high degree of fault-tolerance. To supportthe router, we develop a fault diagnosis and recovery algorithm executed by theBuilt-In Self-Test, self-monitoring, and self-reconfiguration units at runtimeto provide fault-tolerant system functionalities. The Fashion router places norestriction on topology, position or number of faults. It drops 54.3-55.4%fewer nodes for same number of faults (between 30 and 60 faults) in an 8x82D-mesh over other state-of-the-art solutions. It is scalable and efficient.The area overheads are 2.311% and 2.659% when implemented in 8x8 and 16x162D-meshes using the TSMC 65nm library at 1.38GHz clock frequency.

FASHION: Fault-Aware Self-Healing Intelligent On-chip Network