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In the context of embedded systems design, two important challenges are stillunder investigation. First, improve real-time data processing,reconfigurability, scalability, and self-adjusting capabilities of hardwarecomponents. Second, reduce power consumption through low-power designtechniques as clock gating, logic gating, and dynamic partial reconfiguration(DPR) capabilities. Today, several application, e.g., cryptography,Software-defined radio or aerospace missions exploit the benefits of DPR ofprogrammable logic devices. The DPR allows well defined reconfigurable FPGAregion to be modified during runtime. However, it introduces an overhead interm of power consumption and time during the reconfiguration phase. In thispaper, we present an investigation of power consumption overhead of the DPRprocess using a high-speed digital oscilloscope and the shunt resistor method.Results in terms of reconfiguration time and power consumption overhead forVirtex 5 FPGAs are shown.

Accurate Measurement of Power Consumption Overhead During FPGA Dynamic Partial Reconfiguration