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High energy particles from cosmic rays or packaging materials can generate aglitch or a current transient (single event transient or SET) in a logiccircuit. This SET can eventually get captured in a register resulting in a flipof the register content, which is known as soft error or single-event upset(SEU). A soft error is typically modeled as a probabilistic single bit-flipmodel. In developing such abstract fault models, an important issue to consideris the likelihood of multiple bit errors caused by particle strikes. The factthat an SET causes multiple flips is noted in the literature. We perform acharacterization study of the impact of an SET on a logic circuit to quantifythe extent to which an SET can cause multiple bit flips. We use post-layoutcircuit simulations and Monte Carlo sampling scheme to get accurate bit-flipstatistics. We perform our simulations on ISCAS'85, ISCAS'89 and ITC'99benchmarks in 180nm and 65nm technologies. We find that a substantial fractionof SEU outcomes had multiple register flips. We futher analyse the individualcontributions of the strike on a register and the strike on a logic gate, tomultiple flips. We find that, amongst the erroneous outcomes, the probabilityof multiple bit-flips for 'gate-strike' cases was substantial and went up to50%, where as those for 'register-strike' cases was just about 2%. This impliesthat, in principle, we can eliminate the flips due to register strikes usinghardened flip-flop designs. However, in such designs, out of the remainingflips which will be due to gate strikes, a large fraction is likely to bemultiple flips.

Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits