English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

We present the design of a low-power 4-bit 1GS/s folding-flash ADC with afolding factor of two. The design of a new unbalanced double-tail dynamiccomparator affords an ultra-low power operation and a high dynamic range.Unlike the conventional approaches, this design uses a fully matched inputstage, an unbalanced latch stage, and a two-clock operation scheme. Acombination of these features yields significant reduction of the kick-backnoise, while allowing the design flexibility for adjusting the trip points ofthe comparators. As a result, the ADC achieves SNDR of 22.3 dB at 100MHz and21.8 dB at 500MHz (i.e. the Nyquist frequency). The maximum INL and DNL areabout 0.2 LSB. The converter consumes about 700uW from a 1-V supply yielding afigure of merit of 65fJ/conversion step. These attributes make the proposedfolding-flash ADC attractive for the next-generation wireless applications.

A 700uW 1GS/s 4-bit Folding-Flash ADC in 65nm CMOS for Wideband Wireless Communications