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With recent advancing of Internet of Things (IoTs), it becomes veryattractive to implement the deep convolutional neural networks (DCNNs) ontoembedded/portable systems. Presently, executing the software-based DCNNsrequires high-performance server clusters in practice, restricting theirwidespread deployment on the mobile devices. To overcome this issue,considerable research efforts have been conducted in the context of developinghighly-parallel and specific DCNN hardware, utilizing GPGPUs, FPGAs, and ASICs.Stochastic Computing (SC), which uses bit-stream to represent a number within[-1, 1] by counting the number of ones in the bit-stream, has a high potentialfor implementing DCNNs with high scalability and ultra-low hardware footprint.Since multiplications and additions can be calculated using AND gates andmultiplexers in SC, significant reductions in power/energy and hardwarefootprint can be achieved compared to the conventional binary arithmeticimplementations. The tremendous savings in power (energy) and hardwareresources bring about immense design space for enhancing scalability androbustness for hardware DCNNs. This paper presents the first comprehensivedesign and optimization framework of SC-based DCNNs (SC-DCNNs). We firstpresent the optimal designs of function blocks that perform the basicoperations, i.e., inner product, pooling, and activation function. Then wepropose the optimal design of four types of combinations of basic functionblocks, named feature extraction blocks, which are in charge of extractingfeatures from input feature maps. Besides, weight storage methods areinvestigated to reduce the area and power/energy consumption for storingweights. Finally, the whole SC-DCNN implementation is optimized, with featureextraction blocks carefully selected, to minimize area and power/energyconsumption while maintaining a high network accuracy level.

SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing