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Convolutional neural networks (CNNs) have been widely employed in manyapplications such as image classification, video analysis and speechrecognition. Being compute-intensive, CNN computations are mainly acceleratedby GPUs with high power dissipations. Recently, studies were carried outexploiting FPGA as CNN accelerator because of its reconfigurability and energyefficiency advantage over GPU, especially when OpenCL-based high-levelsynthesis tools are now available providing fast verification andimplementation flows. Previous OpenCL-based design only focused on creating ageneric framework to identify performance-related hardware parameters, withoututilizing FPGA's special capability of pipelining kernel functions to minimizememory bandwidth requirement. In this work, we propose an FPGA accelerator witha new architecture of deeply pipelined OpenCL kernels. Data reuse and taskmapping techniques are also presented to improve design efficiency. Theproposed schemes are verified by implementing two representative large-scaleCNNs, AlexNet and VGG on Altera Stratix-V A7 FPGA. We have achieved a similarpeak performance of 33.9 GOPS with a 34% resource reduction on DSP blockscompared to previous work. Our design is openly accessible and thus can bereused to explore new architectures for neural network accelerators.

PipeCNN: An OpenCL-Based FPGA Accelerator for Large-Scale Convolution Neuron Networks