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Compared to conventional general-purpose processors, accelerator-richarchitectures (ARAs) can provide orders-of-magnitude performance and energygains and are emerging as one of the most promising solutions in the age ofdark silicon. However, many design issues related to the complex interactionbetween general-purpose cores, accelerators, customized on-chip interconnects,and memory systems remain unclear and difficult to evaluate.  In this paper we design and implement the ARAPrototyper to enable rapiddesign space explorations for ARAs in real silicons and reduce the tediousprototyping efforts far down to manageable efforts. First, ARAPrototyperprovides a reusable baseline prototype with a highly customizable memorysystem, including interconnect between accelerators and buffers, interconnectbetween buffers and last-level cache (LLC) or DRAM, coherency choice at LLC orDRAM, and address translation support. Second, ARAPrototyper provides a cleaninterface to quickly integrate users' own accelerators written in high-levelsynthesis (HLS) code. The whole design flow is highly automated to generate aprototype of ARA on an FPGA system-on-chip (SoC). Third, to quickly developapplications that run seamlessly on the ARA prototype, ARAPrototyper provides asystem software stack, abstracts the accelerators as software libraries, andprovides APIs for software developers. Our experimental results demonstratethat ARAPrototyper enables a wide range of design space explorations for ARAsat manageable prototyping efforts, which has 4,000X to 10,000X fasterevaluation time than full-system simulations. We believe that ARAPrototyper canbe an attractive alternative for ARA design and evaluation.

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures