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Basic Linear Algebra Subprograms (BLAS) play key role in high performance andscientific computing applications. Experimentally, yesteryear multicore andGeneral Purpose Graphics Processing Units (GPGPUs) are capable of achieving upto 15 to 57% of the theoretical peak performance at 65W to 240W respectivelyfor compute bound operations like Double/Single Precision General MatrixMultiplication (XGEMM). For bandwidth bound operations like Single/Doubleprecision Matrix-vector Multiplication (XGEMV) the performance is merely 5 to7% of the theoretical peak performance in multicores and GPGPUs respectively.Achieving performance in BLAS requires moving away from conventional wisdom andevolving towards customized accelerator tailored for BLAS throughalgorithm-architecture co-design. In this paper, we present acceleration ofLevel-1 (vector operations), Level-2 (matrix-vector operations), and Level-3(matrix-matrix operations) BLAS through algorithm architecture co-design on aCoarse-grained Reconfigurable Architecture (CGRA). We choose REDEFINE CGRA as aplatform for our experiments since REDEFINE can be adapted to support domain ofinterest through tailor-made Custom Function Units (CFUs). For efficientsequential realization of BLAS, we present design of a Processing Element (PE)and perform micro-architectural enhancements in the PE to achieve up-to 74% ofthe theoretical peak performance of PE in DGEMM, 40% in DGEMV and 20% in doubleprecision inner product (DDOT). We attach this PE to REDEFINE CGRA as a CFU andshow the scalability of our solution. Finally, we show performance improvementof 3-140x in PE over commercially available Intel micro-architectures,ClearSpeed CSX700, FPGA, and Nvidia GPGPUs.

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design