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We have designed, fabricated, and successfully tested a prototypemixed-signal, 28x28-binary-input, 10-output, 3-layer neuromorphic network ("MLPperceptron"). It is based on embedded nonvolatile floating-gate cell arraysredesigned from a commercial 180-nm NOR flash memory. The arrays allow precise(~1%) individual tuning of all memory cells, having long-term analog-levelretention and low noise. Each array performs a very fast and energy-efficientanalog vector-by-matrix multiplication, which is the bottleneck for signalpropagation in most neuromorphic networks. All functional components of theprototype circuit, including 2 synaptic arrays with 101,780 floating-gatesynaptic cells, 74 analog neurons, and the peripheral circuitry for weightadjustment and I/O operations, have a total area below 1 mm^2. Its testing onthe common MNIST benchmark set (at this stage, with a relatively low weightimport precision) has shown a classification fidelity of 94.65%, close to the96.2% obtained in simulation. The classification of one pattern takes less than1 us time and ~20 nJ energy - both numbers much better than for digitalimplementations of the same task. Estimates show that this performance may befurther improved using a better neuron design and a more advanced memorytechnology, leading to a >10^2 advantage in speed and a >10^4 advantage inenergy efficiency over the state-of-the-art purely digital (GPU and custom)circuits, at classification of large, complex patterns.

Sub-1-us, Sub-20-nJ Pattern Classification in a Mixed-Signal Circuit Based on Embedded 180-nm Floating-Gate Memory Cell Arrays