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RC4 can be made more secured if an additional RC4-like Post-KSA RandomShuffing (PKRS) process is introduced between KSA and PRGA. It can also be madesignificantly faster if RC4 bytes are processed in a FPGA embedded system usingmultiple coprocessors functioning in parallel. The PKRS process is tuned toform as many S-boxes as required by particular design architectures involvingmultiple coprocessors, each one undertaking byte-by-byte processing. Followinga ecent idea [1] [2] the speed of execution of each processor is also enhancedby another fold if the byte-by-byte processing is replaced by a scheme ofprocessing two consecutive bytes together. Adopting some new innovativeconcepts, three hardware design architectures are proposed in a suitable FPGAembedded system involving 1, 2 and 4 coprocessors functioning in parallel and astudy is made on accelerating RC4 by processing bytes in byte-by-byte modeachieving throughputs from 1-byte-in-1-clock to 4-bytes-in-1-clock. Thehardware designs are appropriately upgraded to accelerate RC4 further byprocessing 2 onsecutive RC4 bytes together and it has been possible to achievea maximum throughput of 8-bytes per clock in Xilinx Virtex-5 LX110t FPGA [3]architecture followed by secured data communication between two FPGA boards.

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock