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Endpoint devices for Internet-of-Things not only need to work under extremelytight power envelope of a few milliwatts, but also need to be flexible in theircomputing capabilities, from a few kOPS to GOPS. Near-threshold(NT) operationcan achieve higher energy efficiency, and the performance scalability can begained through parallelism. In this paper we describe the design of anopen-source RISC-V processor core specifically designed for NT operation intightly coupled multi-core clusters. We introduce instruction-extensions andmicroarchitectural optimizations to increase the computational density and tominimize the pressure towards the shared memory hierarchy. For typicaldata-intensive sensor processing workloads the proposed core is on average 3.5xfaster and 3.2x more energy-efficient, thanks to a smart L0 buffer to reducecache access contentions and support for compressed instructions. SIMDextensions, such as dot-products, and a built-in L0 storage further reduce theshared memory accesses by 8x reducing contentions by 3.2x. With fourNT-optimized cores, the cluster is operational from 0.6V to 1.2V achieving apeak efficiency of 67MOPS/mW in a low-cost 65nm bulk CMOS technology. In a lowpower 28nm FDSOI process a peak efficiency of 193MOPS/mW(40MHz, 1mW) can beachieved.

A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices