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Multi-core, Mixed Criticality Embedded (MCE) real-time systems require hightiming precision and predictability to guarantee there will be no interferencebetween tasks. These guarantees are necessary in application areas such asavionics and automotive, where task interference or missed deadlines could becatastrophic, and safety requirements are strict. In modern multi-core systems,the interconnect becomes a potential point of uncertainty, introducing majorchallenges in proving behaviour is always within specified constraints,limiting the means of growing system performance to add more tasks, or providemore computational resources to existing tasks.  We present MCENoC, a Network-on-Chip (NoC) switching architecture thatprovides innovations to overcome this with predictable, formally verifiabletiming behaviour that is consistent across the whole NoC. We show how thefundamental properties of Benes networks benefit MCE applications and meet ourarchitecture requirements. Using SystemVerilog Assertions (SVA), formalproperties are defined that aid the refinement of the specification of thedesign as well as enabling the implementation to be exhaustively formallyverified. We demonstrate the performance of the design in terms of size,throughput and predictability, and discuss the application level considerationsneeded to exploit this architecture.

A Benes Based NoC Switching Architecture for Mixed Criticality Embedded Systems