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Conventional 2D CMOS technology is reaching fundamental scaling limits, andinterconnect bottleneck is dominating integrated circuit (IC) power andperformance. While 3D IC technologies using Through Silicon Via or MonolithicInter-layer Via alleviate some of these challenges, they follow a similarlayout and routing mindset as 2D CMOS. This is insufficient to address routingrequirements in high-density 3D ICs and even causes severe routing congestionat large-scale designs, limiting their benefits and scalability. Skybridge is arecently proposed fine-grained 3D IC fabric relying on vertical nanowires thatpresents a paradigm shift for scaling, while addressing associated 3Dconnectivity and manufacturability challenges. Skybridge's core fabriccomponents enable a new 3D IC design approach with vertically-composed logicgates, and provide a greater degree of routing flexibility compared toconventional 2D and 3D ICs leading to much larger benefits and futurescalability. In this paper, we present a methodology using relevant metrics toevaluate and quantify the benefits of Skybridge vs. state-of-the-arttransistor-level monolithic 3D IC (T-MI) and 2D in terms of routability and itsimpact on large-scale circuits. This is enabled by a new device-to-systemdesign flow with commercial CAD tools that we developed for large-scaleSkybridge IC designs in 16nm node. Evaluation for standard benchmark circuitsshows that Skybridge yields up to 1.6x lower routing demand against T-MI withno routing congestion (routing demand to resource ratio < 1) at all metallayers. This 3D routability in conjunction with compact vertical gate design inSkybridge translate into benefits of up to 3x lower power and 11x higherdensity over 2D CMOS, while TLM-3DIC approach only has up to 22% power savingand 2x density improvement over 2D CMOS.

Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS