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This paper presents the usage of the Reed Solomon Codes as the Forward ErrorCorrection (FEC) unit of the Hybrid Automatic Repeat Request (ARQ) methods.Parametric and flexible FPGA implementation details of such Erasure-Only RSdecoders with high symbol lengths (e.g. GF(2^32)) have been presented. Thedesign is based on the GF(2m) multiplier logic core operating at a single clockcycle, where the resource utilization and throughput are both directlyproportional to the number of these cores. For a fixed implementation, thethroughput inversely decreases with the number of erasures to be corrected.Implementation in Zynq7020 SoC device of an example GF(2^32)-RS Decoder capableof correcting 64-erasures with a single multiplier resulted in 1641-LUTs and188-FFs achieving 15Mbps, whereas the design with 8 multipliers resulted in6128-LUTs and 628-FFs achieving 100Mbps.

FPGA Impementation of Erasure-Only Reed Solomon Decoders for Hybrid-ARQ Systems