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This paper explains how to develop Verilog hardware description language(HDL) optimized flow graph compiled simulators. It is claimed that the methodsand algorithms described here can be applied in the development of flow graphcompilers for other complex computer languages. The method uses the von Neumanncomputer architecture (MRAM model) as the best abstract model of computationand uses comparison and selection of alternative machine code sequences toutilize modern processor low level parallelism. By using the anti formalistmethod described here, the fastest available full IEEE 1364 2005 Verilog HDLstandard simulators has been developed. The compiler only required 95,000 linesof C code and two developers. This paper explains how such a compiled simulatorvalidates the anti-formalism computer science methodology best expressed byPeter Naur's datalogy and provides specific guidelines for applying the method.Development history from a slow interpreter into a fast flow graph basedmachine code compiled simulator is described. The failure of initial effortsthat tried to convert a full 1364 compliant interpreter into interpretedexecution of possibly auto generated virtual machines is discussed. Theargument that fast Verilog simulation requires detail removing abstraction isshown to be incorrect. Reasons parallel GPU Verilog simulation has notsucceeded are given.

CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple