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Current-induced domain wall motion (CIDWM) is regarded as a promising waytowards achieving emerging high-density, high-speed and low-power non-volatiledevices. Racetrack memory is an attractive spintronic memory based on thisphenomenon, which can store and transfer a series of data along a magneticnanowire. However, storage capacity issue is always one of the most seriousbottlenecks hindering its application for practical systems. This paper focuseson the potential of racetrack memory towards large capacity. The investigationscovering from device level to system level have been carried out. Variousalternative mechanisms to improve the capacity of racetrack memory have beenproposed and elucidated, e.g. magnetic field assistance, chiral DW motion andvoltage-controlled flexible DW pinning. All of them can increase nanowirelength, allowing enhanced feasibility of large-capacity racetrack memory. Byusing SPICE compatible racetrack memory electrical model and commercial CMOS 28nm design kit, mixed simulations are performed to validate theirfunctionalities and analyze their performance. System level evaluationsdemonstrate the impact of capacity improvement on overall system. Compared withtraditional SRAM based cache, racetrack memory based cache shows its advantagesin terms of execution time and energy consumption.

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System