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Modern DRAM cells are periodically refreshed to prevent data loss due toleakage. Commodity DDR DRAM refreshes cells at the rank level. This degradesperformance significantly because it prevents an entire rank from servingmemory requests while being refreshed. DRAM designed for mobile platforms,LPDDR DRAM, supports an enhanced mode, called per-bank refresh, that refreshescells at the bank level. This enables a bank to be accessed while another inthe same rank is being refreshed, alleviating part of the negative performanceimpact of refreshes. However, there are two shortcomings of per-bank refresh.First, the per-bank refresh scheduling scheme does not exploit the fullpotential of overlapping refreshes with accesses across banks because itrestricts the banks to be refreshed in a sequential round-robin order. Second,accesses to a bank that is being refreshed have to wait.  To mitigate the negative performance impact of DRAM refresh, we propose twocomplementary mechanisms, DARP (Dynamic Access Refresh Parallelization) andSARP (Subarray Access Refresh Parallelization). The goal is to address thedrawbacks of per-bank refresh by building more efficient techniques toparallelize refreshes and accesses within DRAM. First, instead of issuingper-bank refreshes in a round-robin order, DARP issues per-bank refreshes toidle banks in an out-of-order manner. Furthermore, DARP schedules refreshesduring intervals when a batch of writes are draining to DRAM. Second, SARPexploits the existence of mostly-independent subarrays within a bank. Withminor modifications to DRAM organization, it allows a bank to serve memoryaccesses to an idle subarray while another subarray is being refreshed.Extensive evaluations show that our mechanisms improve system performance andenergy efficiency compared to state-of-the-art refresh policies and the benefitincreases as DRAM density increases.

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses