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In this paper we use the Adapteva Epiphany manycore chip to demonstrate howthe throughput and the latency of a baseband signal processing chain, typicallyfound in LTE or WiFi, can be optimized by a combination of task- and dataparallelization, and data pipelining. The parallelization and data pipeliningare facilitated by the shared memory architecture of the Epiphany, and the factthat a processor on one core can write directly into the memory of any othercore on the chip.

Improving Latency in a Signal Processing System on the Epiphany Architecture