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On-chip voltage regulation using distributed Digital Low Drop Out (LDO)voltage regulators has been identified as a promising technique for efficientpower-management for emerging multi-core processors. Digital LDOs (DLDO) canoffer low voltage operation, faster transient response, and higher currentefficiency. Response time as well as output voltage ripple can be reduced byincreasing the speed of the dynamic comparators. However, the comparator offsetsteeply increases for high clock frequencies, thereby leading to enhancedvariations in output voltage. In this work we explore the design of digitalLDOs with multiple dynamic comparators that can overcome this bottleneck. Inthe proposed topology, we apply time-interleaved comparators with the samevoltage threshold and uniform current step in order to accomplish theaforementioned features. Simulation based analysis shows that the DLDO withtime-interleaved comparators can achieve better overall performance in terms ofcurrent efficiency, ripple and settling time. For a load step of 50mA, a DLDOwith 8 time-interleaved comparators could achieve an output ripple of less than5mV, while achieving a settling time of less than 0.5us. Load current dependantdynamic adjustment of clock frequency is proposed to maintain high currentefficiency of ~97%.

Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple