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Spin Transfer Torque MRAMs are attractive due to their non-volatility, highdensity and zero leakage. However, STT-MRAMs suffer from poor reliability dueto shared read and write paths. Additionally, conflicting requirements for dataretention and write-ability (both related to the energy barrier height of themagnet) makes design more challenging. Furthermore, the energy barrier heightdepends on the physical dimensions of the free layer. Any variations in thedimensions of the free layer lead to variations in the energy barrier height.In order to address poor reliability of STT-MRAMs, usage of Error CorrectingCodes (ECC) have been proposed. Unlike traditional CMOS memory technologies,ECC is expected to correct both soft and hard errors in STT_MRAMs. To achieveacceptable yield with low write power, stronger ECC is required, resulting inincreased number of encoded bits and degraded memory efficiency. In this paper,we propose Failure aware ECC (FaECC), which masks permanent faults whilemaintaining the same correction capability for soft errors without increasedencoded bits. Furthermore, we investigate the impact of process variations onrun-time reliability of STT-MRAMs. We provide an analysis on the impact ofprocess variations on the life-time of the free layer and retention failures.In order to analyze the effectiveness of our methodology, we developed across-layer simulation framework that consists of device, circuit and arraylevel analysis of STT-MRAM memory arrays. Our results show that using FaECCrelaxes the requirements on the energy barrier height, which reduces the writeenergy and results in smaller access transistor size and memory array area.Keywords: STT-MRAM, reliability, Error Correcting Codes, ECC, magnetic memory

Yield, Area and Energy Optimization in Stt-MRAMs using failure aware ECC