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Offloading compute intensive nested loops to execute on FPGA acceleratorshave been demonstrated by numerous researchers as an effective performanceenhancement technique across numerous application domains. To construct suchaccelerators with high design productivity, researchers have increasinglyturned to the use of overlay architectures as an intermediate generation targetbuilt on top of off-the-shelf FPGAs. However, achieving the desiredperformance-overhead trade-off remains a major productivity challenge ascomplex application-specific customizations over a large design space coveringmultiple architectural parameters are needed.  In this work, an automatic nested loop acceleration framework utilizing aregular soft coarse-grained reconfigurable array (SCGRA) overlay is presented.Given high-level resource constraints, the framework automatically customizesthe overlay architectural design parameters, high-level compilation options aswell as communication between the accelerator and the host processor foroptimized performance specifically to the given application. In ourexperiments, at a cost of 10 to 20 minutes additional tools run time, theproposed customization process resulted in up to 5 times additional speedupover a baseline accelerator generated by the same framework withoutcustomization. Overall, when compared to the equivalent software running on thehost ARM processor alone on the Zedboard, the resulting accelerators achievedup to 10 times speedup.

Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay