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Modern SoC-FPGA that consists of FPGA with embedded ARM cores is beingpopularized as an embedded vision system platform. However, the design approachof SoC-FPGA applications still follows traditional hardware-software separateworkflow, which becomes the barrier of rapid product design and iteration onSoC-FPGA. High-Level Synthesis (HLS) and OpenCL-based system-level designapproaches provide programmers the possibility to design SoC-FGPA atsystem-level with an unified development environment for both hardware andsoftware. To evaluate the feasibility of high-level design approach especiallyfor embedded vision applications, Vivado HLS and Altera SDK for OpenCL,representative and most popular commercial tools in market, are selected asevaluation design tools, disparity map calculation as targeting application. Inthis paper, hardware accelerators of disparity map calculation are designedwith both tools and implemented on Zedboard and SoCKit development board,respectively. Comparisons between design tools are made in aspects ofsupporting directives, accelerator design process, and generated hardwareperformance. The results show that both tools can generate efficient hardwarefor disparity map calculation application with much less developing time.Moreover, we can also state that, more directives (e.g., interface type, arrayreshape, resource type specification) are supported, but more hardwareknowledge is required, in Vivado HLS. In contrast, Altera SDK for OpenCL isrelatively easier for software programmers who is new to hardware, but with theprice of more resources usage on FPGA for similar hardware acceleratorgeneration.

A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example