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The well known method C-Slow Retiming (CSR) can be used to automaticallyconvert a given CPU into a multithreaded CPU with independent threads. TheseCPUs are then called streaming or barrel processors. System Hyper Pipelining(SHP) adds a new flexibility on top of CSR by allowing a dynamic number ofthreads to be executed and by enabling the threads to be stalled, bypassed andreordered. SHP is now applied on the programming elements (PE) of acoarse-grained reconfigurable architecture (CGRA). By using SHP, moreperformance can be achieved per PE. Fork-Join operations can be implemented ona PE using the flexibility provided by SHP to dynamically adjust the number ofthreads per PE. Multiple threads can share the same data locally, which greatlyreduces the data traffic load on the CGRA's routing structure. The paper showsthe results of a CGRA using SHP-ed RISC-V cores as PEs implemented on a FPGA.

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA