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The algorithm-to-hardware High-level synthesis (HLS) tools today arepurported to produce hardware comparable in quality to handcrafted designs,particularly with user directive driven or domains specific HLS. However, HLStools are not readily equipped for when an application/algorithm needs toscale. We present a (work-in-progress) semi-automated framework to mapapplications over a packet-switched network of modules (single FPGA) and thento seamlessly partition such a network over multiple FPGAs over quasi-seriallinks. We illustrate the framework through three application case studies: LDPCDecoding, Particle Filter based Object Tracking, and Matrix VectorMultiplication over GF(2). Starting with high-level representations of eachcase application, we first express them in an intermediate message passingformulation, a model of communicating processing elements. Once the processingelements are identified, these are either handcrafted or realized using HLS.The rest of the flow is automated where the processing elements are plugged onto a configurable network-on-chip (CONNECT) topology of choice, followed bypartitioning the 'on-chip' links to work seamlessly across chips/FPGAs.

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies