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In this paper we will present various hardware architecture designs forimplementing the SIMON 64/128 block cipher as a cryptographic componentoffering encryption, decryption and self-contained key-scheduling capabilitiesand discuss the issues and design options we encountered and the tradeoffs wemade in implementing them. Finally, we will present the results of our hardwarearchitectures' implementation performances on the Xilinx Spartan-6 FPGA series.

Simple SIMON: FPGA implementations of the SIMON 64/128 Block Cipher