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We present a hardware architecture that uses the Neural Engineering Framework(NEF) to implement large-scale neural networks on Field Programmable GateArrays (FPGAs) for performing pattern recognition in real time. NEF is aframework that is capable of synthesising large-scale cognitive systems fromsubnetworks. We will first present the architecture of the proposed neuralnetwork implemented using fixed-point numbers and demonstrate a routine thatcomputes the decoding weights by using the online pseudoinverse update method(OPIUM) in a parallel and distributed manner. The proposed system isefficiently implemented on a compact digital neural core. This neural coreconsists of 64 neurons that are instantiated by a single physical neuron usinga time-multiplexing approach. As a proof of concept, we combined 128 identicalneural cores together to build a handwritten digit recognition system using theMNIST database and achieved a recognition rate of 96.55%. The system isimplemented on a state-of-the-art FPGA and can process 5.12 million digits persecond. The architecture is not limited to handwriting recognition, but isgenerally applicable as an extremely fast pattern recognition processor forvarious kinds of patterns such as speech and images.

A neuromorphic hardware architecture using the Neural Engineering Framework for pattern recognition