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At sub-20nm technologies CMOS scaling faces severe challenges primarily dueto fundamental device scaling limitations, interconnection overhead and complexmanufacturing. Migration to 3D has been long sought as a possible pathway tocontinue scaling, however, intrinsic requirements of CMOS are not compatiblefor fine-grained 3D integration. We proposed a truly fine-grained 3D integratedcircuit fabric called Skybridge that solves nanoscale challenges and achievesorders of magnitude benefits over CMOS. In Skybridge, device, circuit,connectivity, thermal management and manufacturing issues are addressed in anintegrated 3D compatible manner. At the core of Skybridge assembly are uniformvertical nanowires, which are functionalized with architected features forfabric integration. All active components are created primarily usingsequential material deposition steps on these nanowires. Lithography and dopingare performed prior to any functionalization and their precision requirementsare significantly reduced. This paper introduces Skybridge manufacturingpathway that is developed based on extensive process, device simulations andexperimental metrology, and uses established processes. Experimentaldemonstrations of key process steps are also shown.

Manufacturing Pathway and Experimental Demonstration for Nanoscale Fine-Grained 3-D Integrated Circuit Fabric