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We present the TyTra-IR, a new intermediate language intended as acompilation target for high-level language compilers and a front-end for HDLcode generators. We develop the requirements of this new language based on thedesign-space of FPGAs that it should be able to express and theestimation-space in which each configuration from the design-space should bemappable in an automated design flow. We use a simple kernel to illustratemultiple configurations using the semantics of TyTra-IR. The key novelty ofthis work is the cost model for resource-costs and throughput for differentconfigurations of interest for a particular kernel. Through the realisticexample of a Successive Over-Relaxation kernel implemented both in TyTra-IR andHDL, we demonstrate both the expressiveness of the IR and the accuracy of ourcost model.

An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs