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This paper proposes a "quasi-synchronous" design approach for signalprocessing circuits, in which timing violations are permitted, but without theneed for a hardware compensation mechanism. The case of a low-densityparity-check (LDPC) decoder is studied, and a method for accurately modelingthe effect of timing violations at a high level of abstraction is presented.The error-correction performance of code ensembles is then evaluated usingdensity evolution while taking into account the effect of timing faults.Following this, several quasi-synchronous LDPC decoder circuits based on theoffset min-sum algorithm are optimized, providing a 23%-40% reduction in energyconsumption or energy-delay product, while achieving the same performance andoccupying the same area as conventional synchronous circuits.

Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations