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The paper describes the design and hardware implementation of 32-bitencrypted MIPS processor based on MIPS pipeline architecture. The organizationof pipeline stages in such a way that pipeline can be clocked at highfrequency. Encryption and Decryption blocks of data encryption standard (DES)cryptosystem and dependency among themselves are explained in detail with thehelp of block diagram. In order to increase the processor functionality andperformance, especially for security applications we include three newinstructions 32-bit LKLW, LKUW and CRYPT. The design has been synthesized at40nm process technology targeting using Xilinx Virtex-6 device. The encryptedMIPS pipeline processor can work at 218MHz at synthesis level and 744MHz atsimulation level.

Efficient Hardware Design and Implementation of Encrypted MIPS Processor