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Fast Fourier transform (FFT) of large number of samples requires hugehardware resources of field programmable gate arrays (FPGA), which needs morearea and power. In this paper, we present an area efficient architecture of FFTprocessor that reuses the butterfly elements several times. The FFT processoris simulated using VHDL and the results are validated on a Virtex-6 FPGA. Theproposed architecture outperforms the conventional architecture of a $N$-pointFFT processor in terms of area which is reduced by a factor of $log_N 2$ withnegligible increase in processing time.

A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation