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The deep trapping gate pixel device was described recently as an alternativeto CMOS 3T pixel. The feasibilty of this device was studied with technologicaland transport simulations used in classical electron devices and processdesign. A buried gate containing localized deep level centers (Deep TrappingGate or DTG) is the key for the operation of this field effect pixel detector.This can be made with deep levels or a quantum box. This buried gate canmodulates the drain-source current, the same way the upper gate does. Thisprinciple was evaluated with realistic simulations physical parameters and thisshows that the signal magnitude is sufficient for an energy deposition of aMinimum Ionizing Particle within a limited silicon thickness (a few microns).We will study here the potential techniques usable for the fabrication of thedevice with their drawbacks, advantages and limits. The first techniqueintroduced is impurity implantation, followed by annealing. The problemsrelated to the control of the defects in the DTG will be examined in the lightof recent work on ion implantation. As an alternative recent work on quantumdots opens the possibility to the use Ge dots as a DTG. Ion implantation canagain be used with some limitations. As an alternative to ion implantation anepitaxial DTG could be fabricated using standard techniques. The firstconclusion of this study is that all the established techniques necessary forthe development of the DTG pixel can reasonably be successful because therelated bottlenecks may be overcome. The deep levels concentration in the DTG(above 10^18 cm-3) is higher than the concentration of radiation induceddefects for integrated fluences lower than 1x10^16 cm-3.

Silicon MOS Pixel Based on the Deep Trapping Gate Principle: Design and Material Science Challenges