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Quantum computers are exponentially faster than their classical counterpartsin terms of solving some specific, but important problems. The biggestchallenge in realizing a quantum computing system is the environmental noise.One way to decrease the effect of noise (and hence, reduce the overhead ofbuilding fault tolerant quantum circuits) is to reduce the latency of thequantum circuit that runs on a quantum circuit. In this paper, a novelalgorithm is presented for scheduling, placement, and routing of a quantumalgorithm, which is to be realized on a target quantum circuit fabrictechnology. This algorithm, and the accompanying software tool, advancesstate-of-the-art in quantum CAD methodologies and methods while considering keycharacteristics and constraints of the ion-trap quantum circuit fabric.Experimental results show that the presented tool improves results of theprevious tool by about 41%.

Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric