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This study proposes a new router architecture to improve the performance ofdynamic allocation of virtual channels. The proposed router is designed toreduce the hardware complexity and to improve power and area consumption,simultaneously. In the new structure of the proposed router, all of thecontrolling components have been implemented sequentially inside the allocatorrouter modules. This optimizes communications between the controllingcomponents and eliminates the most of hardware overloads of modularcommunications. Eliminating additional communications also reduces the hardwarecomplexity. In order to show the validity of the proposed design in realhardware resources, the proposed router has been implemented onto aField-Programmable Gate Array (FPGA). Since the implementation of aNetwork-on-Chip (NoC) requires certain amount of area on the chip, thesuggested approach is also able to reduce the demand of hardware resources. Inthis method, the internal memory of the FPGA is used for implementing controlunits. This memory is faster and can be used with specific patterns. The use ofthe FPGA memory saves the hardware resources and allows the implementation ofNoC based FPGA.

Performance Enhancement of Routers in Networks-on-Chip Using Dynamic Virtual Channels Allocation