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In the context of mapping high-level algorithms to hardware, we consider thebasic problem of generating an efficient hardware implementation of a singlethreaded program, in particular, that of an inner loop. We describe acontrol-flow mechanism which provides dynamic loop-pipelining capability inhardware, so that multiple iterations of an arbitrary inner loop can be madesimultaneously active in the generated hardware, We study the impact of thisloop-pipelining scheme in conjunction with source-level loop-unrolling. Inparticular, we apply this technique to some common loop kernels: regularkernels such as the fast-fourier transform and matrix multiplication, as wellas an example of an inner loop whose body has branching. The resultingresulting hardware descriptions are synthesized to an FPGA target, and thencharacterized for performance and resource utilization. We observe that the useof dynamic loop-pipelining mechanism alone typically results in a significantimprovements in the performance of the hardware. If the loop is staticallyunrolled and if loop-pipelining is applied to the unrolled program, then theperformance improvement is still substantial. When dynamic loop pipelining isused in conjunction with static loop unrolling, the improvement in performanceranges from 6X to 20X (in terms of number of clock cycles needed for thecomputation) across the loop kernels that we have studied. These optimizationsdo have a hardware overhead, but, in spite of this, we observe that the jointuse of these loop optimizations not only improves performance, but also theperformance/cost ratio of the resulting hardware.

Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware